A Novel Method of SOT-MRAM Switching

Three-terminal memory cell structures based on a magnetic tunnel junction (MTJ) are promising candidates for future generations of magnetic memory [1]. In particular, three-terminal devices with spin-orbit torque (SOT) switching have already been proposed [2]. Typically, a SOT memory cell is an MTJ fabricated on a heavy metal channel with large spin-orbit interaction, wherein the free layer is in direct contact with the heavy metal channel. Spin torque generated by a current through the channel induces the magnetization switching. However, one shortcoming is that an external magnetic field is required to provide deterministic switching [3]. The second shortcoming of this memory type compared to the conventional spin transfer torque memory is that it demands more space and thus leads to a lower area density because of the second transistor required for writing [1]. In this work we propose an external magnetic field free method of soft magnetic layer switching based on two consecutive orthogonal sub-nanosecond in-plane current pulses. We investigate the proposed method by means of extensive micromagnetic simulations and discuss a possibility of using this method in building 1Transistor-1MTJ memory cells in a cross-point architecture. In the proposed method the soft magnetic layer switching is governed by the torques generated in the metal channel by charge currents (Fig.1). The first pulse is necessary for tilting the magnetization of the free layer from its stable state in order to create a small initial angle. The second pulse is used for switching the free layer to a new state (Fig.2). As our simulations show (Fig.3a), the switching probability for the proposed write scheme is 1, when the second pulse width is in the range 2.63-9.1ns. Furthermore, we demonstrated the absence of switching in the case of using only one of the two pulses, as this switching is an unwanted event and leads to the loss of information in half-selected cells in a cross-point architecture (Fig.3b, Fig.3c). Finally, potential memory cells architectures with this switching method are shown in Fig.4.